The System-On-Chip Lite (SoCLite) concept is to provide a customised system, without the high NRE cost, development effort and system verification usually attached to System-On-Chip designs.

Click here for SoCLite

The System-on-Chip Lite+ (SoCLite+) provides a complete microcontroller subsystem consisting of an ARM7TDMI-S CPU core, a multi-port memory controller, a 10/100M Ethernet MAC and several peripherals.

The single-chip System-on-Chip Lite+ device also contains a Gate Array area for user defined logic (UDL) that allows implementation of proprietary and application-specific functions.

The System-on-Chip Lite+ microcontroller subsystem is fully developed and pre-verified. This means the developer is freed from the task of producing a microcontroller subsystem from scratch.

Instead the efforts can be focused connecting the custom or application-specific function blocks in the UDL area to the microcontroller subsystem via the AMBA bus systems (AHB for high speed or APB for peripherals).

The important part, however, of the System-on-Chip Lite+ microcontroller subsystem is the memory subsystem. The primary goal here is to achieve minimum latency for memory access in order to fully exploit the performance of the ARM7TDMI-S CPU core. On the ARM7TDMI-S side, there is a specified interface that also allows IP macro blocks from third-party suppliers to be integrated easily into the System-on-Chip Lite+ device.

System-on-Chip Lite+ features:

• ARM® subsystem

  • ARM7TDMI-STM core

  • 32-bit ARM® and 16-bit Thumb® instruction set

  • 32-bit x 8-bit multiplier

  • SRAM: 8 Kbytes

  • Mask ROM: 3 Kbytes

  • Operating frequency: up to 66 MHz

  • 10/100M EthernetTM Media Access Controller (MAC)

  • Multi-port memory controller supporting:

  • SDRAM (100 MHz), Flash (standard/page mode), SRAM, ROM

  • Programmable interrupt controller

  • 32 interrupts, 8 priority levels

  • Peripherals: UART, timer, reset, watchdog

  • JTAG interface for debug and boundary scan

   

• UDL area for custom function integration

  • Sea-of-gates type 0.25µm gate array ASIC architecture

  • Two UDL size options:

  • Option A: up to 250K raw gates

  • Option B: up to 440K raw gates

  • AHB & APB interconnect to the ARM7TDMI-S subsystem

   

• Device specification

  • Operating voltage: 2.5 V ±0.25 V

  • I/O voltage: 2.5 V, 3.3V and 5 V compatible

  • Temperature range: -40 to +85 °C

   

• Packages:

  • 240-pin FPBGA for UDL option A

  • 256-pin BGA for UDL option B

The SOCLite+ development board represents the functional equivalent of the final single chip solution.

It can be used for in system verification, long before the real silicon is manufactured. It also allows for software development to be started at a very early stage.

The ARM7 based microcontroller system is in the SOCLite+ prototype device and the UDL is represented by a Stratix Altera FPGA. Both are interconnected with the AHB and APB AMBA buses, just like the final devices

All necessary signals are routed to connectors for verification and debugging purposes within the final system.

Once the design has been fully evaluated using the development board, the conversion to a System-On-Chip Lite+ device follows an FPGA to Gate Array conversion flow with full support from NEC.

- The design environment is fully supported by NEC's OpenCADTM
- Fast and easy gate array design flow for user logic.
- Model of the ARM© subsystem used for logic simulation.

The end product is a single chip solution for a customised microcontroller without the usual risk and cost of a full System On Chip solution.

Operating Systems support for System-on-Chip Lite+

The ARM7 core integrated in System-on-Chip Lite+ can execute the operating systems available for this processor. Customers already deploying ARM7 systems need make no changes. NEC Electronics supports several operating systems, including µC Linux. Other ARM-typical operating systems such as the ones from Enea Embedded Technology and from Segger are also supported. A TCP/IP stack is available in all cases.

Documentation:

• SoC-Lite+ Product Letter - 38kB -

• Development Board Data - 68kB -

• Design Flow Introduction - 66kB -

• Pamphlet SoCLite+ - 386kB -

---