It includes a pre-verified ARM^© subsystem and an area of logic which can be customised for the application.

The ARM7TDMI^TM 32 bits core and its subsystem are fully designed. It frees the user from developing a complete system on chip. The basic functions are included in the sub-system and special blocks (functions or extra peripherals) are implemented in the UDL (User Defined Logic).

The development effort and system verification usually linked to a full System On Chip design are reduced tremendously. The turn around time is short and the NRE cost is very low.

SoC-Lite Block Diagram

• 32 bits ARM^© core and 16 bit Thumb instruction set.
• APB (ARM^© Peripheral Bus) interconnects the different blocks and the UDL.
• UDL consists of 190k raw gates.

The basic functions implemented are:

• 32 bits x 8 bits multiplier.
• UART
• 32 bits Timer
• Programmable Interrupt Controller
• Reset Watchdog
• PLL
• Clock Generator
• 8 kbytes of SRAM are available on chip.
• 2 kbytes of Bootstrap ROM.
• Additional memory components (SRAM, ROM or Flash) can be accessed through the memory controller.
• JTAG test and debug interface.

A development board is available to enable the customer to test the functionality of the customised UDL part in an external FPGA together with the ARM^© subsystem.

This board provides the same function blocks as your final SoClite chip and enables you to start immediately to build up your system.

All interconnects between the CPU subsystem and the UDL are available on test pins. The UDL is evaluated with an SRAM-based FPGA. Two versions are available: either using a Xilinx© Virtex^TM FPGA or an Altera^© Apex^TM. External memory is also present on the board.

The UART and the debug function of the ARM7TDMI^TM development tools are supported with special debugging connectors.

Once the design has been fully evaluated using the development board, the conversion to a System-On-Chip Lite device follows an FPGA to Gate Array conversion flow with full support from NEC.

• The design environment is fully supported by NEC's OpenCAD^TM
• Fast and easy gate array design flow for user logic.
• Model of the ARM^© subsystem used for logic simulation.

The end product is a single chip solution for a customised microcontroller without the usual risk and cost of a full System On Chip solution.

Documentation:

• SoC-Lite Product Letter - 72kB -
• Development Board Data - 57kB -
• Design Flow Introduction - 56kB -