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NEC's ISSP (Instant Solution Silicon Platform) technology combines performance and functionality benefits of a cell based ASIC with reduced cost and short design time of Gate Arrays. |
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NEC's ISSP (Instant Solution Silicon Platform) technology combines performance and functionality benefits of a cell based ASIC with reduced cost and short design time of Gate Arrays. |
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NEC provides in this new field of structured ASICs with two processes ISSP1 with 150nm (ITRS technology node) (0.13µm drawn gate length) and ISSP90 with 90nm technology node (0.065µm drawn gate length). Further details can be found on the ISSP Technology page. Finish designs in record time using best-in-class EDA tools certified by NEC Electronics for ISSP with the special design flow. ISSP1 There are 2 grades for this family:
ISSP1-STD provides high performance, up to 250 MHz at low power dissipation, that you can expect from a 0.13 µm technology. Design for testability (DFT), clock-tree-synthesis (CTS) and measures to avoid DSM-Effects are already taken care of. Hence the design effort and focus is on the application and is freed from these tasks.
The ISSP1-HSI range makes use of the process-proven SERDES cores. Frequencies range from 622MHz through 1.25Gbps and 2.5Gbps to fulfill individual application requirements. Gigabit Ethernet and Fibrechannel, PCI-Express interfaces can be supported with this core.
ISSP90 2 Grades HD and HSI (For High Speed Interface) The ISSP90 series of structured ASICs is based on
the company's 90-nanometer (UX6) technology. The ISSP90 devices by far exceed the performance and integration of today's most advanced FPGAs, while still delivering the fast turnaround time (TAT) and low non-recurring engineering (NRE) costs associated with NEC's initial ISSP offering. For the new ISSP90 devices a 10 Gigabit-per-second (Gbps) single-port SerDes interface, as well as a next-generation 3-Gbps Serial-ATA interface will be incorporated, making the devices ideal for high-end computing and high-bandwidth networking applications.
ISSP Design Flow Leveraging ISSPs extensive set of embedded resources, the ISSP design flow smoothes the way of timing closure so you get silicon fast - even when you are pushing performance to the maximum. Further enhancing the ISSP design flow is the ability to use the EDA industry´s leading tools. Via the ISSP EDA vendor alliance, NEC Electronics has certified tools from a number of vendors support the specific configurations of ISSP. These tools implement multiple ISSP design flows, so you can choose the tools that best suit your design style and application requirements.
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