Main features of the CB-12-series

Main features of the CB-12-series

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1. Choice of Four Libraries To Meet Exacting Customer Requirements:

Target:	Library:	Operating Frequency:
Low power consumption:	L	Up to 100MHz
Standard performance:	M	100-250MHz
High speed performance:	HM	250-450MHz
Ultra high speed performance:	H	450MHz+

2. 4T SRAM:

4 transistor SRAM macro currently in development will enable reduced embedded SRAM surface area by up to 30% compared to current 6T SRAM.

3. Optimized Line-up of IP Cores:

Library: Core:

L library: V850E etc.

M library: DSP etc.

HM library: VR-series etc.

Other cores and system IP in development for optimized solutions.

Please see IP Core Lineup for the CB-12) for further details.

Click to read the official NEC press release on CB-12 family.

4. Deep integration, high operating frequencies, low power consumption:

Integration of up to 32 million, 2-input NAND compatible gates.
Power supply of just 1.5V, delay time is just 11.1 pico seconds (Fan out 2) using HM library.
Power consumption is a measly 7.3nW per 1MHz per gate when using low power consumption L library, or approximately half that achieved with NEC's previous products.

5. Leading-edge Packaging:

A full range of packaging for large pin counts, from flip-chip packaging to chip size packaging (CSP) and standard packages including:

Package:	Pin count:
PBGA:	max. 672 pins
TBGA:	max. 1088 pins
QFP:	max. 376 pins (0.4mm pitch)
Flip-chip:	max. 3,000 pins
CSP:	max. 600 pins

IP Core Lineup for the CB-12

1. Memory Macros (SRAM)

Includes both bit/word customizable 6Tr cell-type common in compiled-type memory in current cell-based ICs and loadless 4Tr cell-type indispensable for high density memory in system LSIs.

High speed memory (compiled)	1 port: 4K word x 36-bit (Tcyc=2.0ns @ 1Kw x 36b) 2 port: 4k word x 72 bit (Tcyc=2.5ns @ 2Kw x 16b)
High integration memory (compiled)	1 port: 64K word x 36 bit (Tcyc=4.0ns @ 32Kw x 16b)
High density memory (loadless 4Tr cell)	1 port: 4Mb, 8Mbit

2. Core lineup

0.13-micron CMOS high integration, high frequency, low power consumption cores for system LSI applications (includes those currently in development

PC:	PCI^1 controller, USB^2, IEEE1394
Consumer:	V850E CPU^3, VRxxxx-series CPU^4, MPEG-2 encoder/decoder, AD converter, DA converter, modem CODEC
Mobile:	DSP, audio CODEC
Network:	ATM (25M, 155MHz), Ethernet 10/100Base/1Gbps, ADSL^5, VDSL^6
Graphics:	DRAC^*7, 2D/3D accelerator, NTSC/PAL encoder
Common IP:	Digital PLL, analog PLL, UART^*8 register file, scan, JTAG, FIFO, CAM, ROM, DRAM, Flash

3. Interface

Although the internal power supply is 1.5V, full swing interface I/O buffers for 2.5V and 3.3V hare also been prepared. In addition to standard CMOS interface blocks, additional high-speed interfaces include:

I/O Block:	LVCMOS/LVTTL low noise buffer (through rate buffer), 3 state buffer, open drain buffer
High-speed interface:	GTL+^9, HSTL^10, pECL^11, SSTL^12, LVDS^13, AGP^14, PCI, USB, IEEE1394

*1: Interface standard proposed by Intel Corporation (Peripheral Component Interconnect)

*2: Universal Serial Bus

*3: NEC's 32-bit RISC MPU

*4: NEC's 64-bit RISC MPU

*5: Asymmetric Digital Subscriber Line

*6: Very high bit rate Digital Subscriber Line

*7: Direct Rambus ASIC cell

*8: Universal Asynchronous Receiver Transmitter

*9: Interface standard proposed by Intel Corporation (Gunning Transceiver Logic)

*10: High Speed Transceiver Logic

*11: Pseudo Emitter Coupled Logic

*12: Stub Series Terminated Transfer Logic

*13: Low Voltage Differential Signaling

*14: Accelerated Graphics Port

Main specifications for the CB-12 series

Process technology:	0.13-micron, Si gate CMOS, Aluminum (Cu) 5/7/8^*1 metal layers
Max gate count:	32 million gates (L,M)
Max I/O^*2:	2,700
Power supply:	1.5V internal, 2.5/3.3V I/O buffer
Power consumption:	7.3nW/MHz/gate (using L library)
Delay time - inverter:	11.1 pico seconds (Fan out 2) (using HM library)
Delay time - 2NAND:	15.9 pico seconds (Fan out 2) (using HM library)
Output drive input:	Max 24 milliA
Interface:	2.5/3.3V interface low-noise buffer high-speed interface (PCI-X, HSTL, LVDS, GTL+, AGP etc.)
RAM macro:	Single port, dual port SRAM (embedded type), FIFO, CAM, ROM, DRAM, Flash
Cores:	CPU (VRxxxx-series, V850E-series), AD converter, DA converter, DSP, PCI, USB, IEEE1394 etc., scan, JTAG etc.

*1: When using 8 metal layers, uses pad from flip chip package

*2: The number of usable pins depends on the package used.

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Library:	Core:
L library:	V850E etc.
M library:	DSP etc.
HM library:	VR-series etc.

*1:	Interface standard proposed by Intel Corporation (Peripheral Component Interconnect)
*2:	Universal Serial Bus
*3:	NEC's 32-bit RISC MPU
*4:	NEC's 64-bit RISC MPU
*5:	Asymmetric Digital Subscriber Line
*6:	Very high bit rate Digital Subscriber Line
*7:	Direct Rambus ASIC cell
*8:	Universal Asynchronous Receiver Transmitter
*9:	Interface standard proposed by Intel Corporation (Gunning Transceiver Logic)
*10:	High Speed Transceiver Logic
*11:	Pseudo Emitter Coupled Logic
*12:	Stub Series Terminated Transfer Logic
*13:	Low Voltage Differential Signaling
*14:	Accelerated Graphics Port

*1:	When using 8 metal layers, uses pad from flip chip package
*2:	The number of usable pins depends on the package used.